Vertical interconnects are a necessary component in a microelectronic logic circuit, and in any device where an electrical connection is required between conducting layers within a multilayered substrate. An electrical connection may be required between the top pixel of the device and the drain electrode on the lower level of the device.
It is known to form a hole through a structure including a plurality of layers by the action of successively ablating the layers using a laser operating at a wavelength at which the layers have a high optical density. Laser ablation techniques are described in JP2297932, U.S. Pat. No. 4,894,115, EP0436320, and WO9820531.
For example, where the structure includes one or more layers of a material having a high energy gap, it is known to ablate a hole through such a structure using a laser at the short wavelengths (UV wavelengths) which such material readily absorb.
An objective of the present invention is to provide a new technique for forming holes using laser energy.